1. Field
Aspects in accordance with the present application relate to a latch circuit and an electronic device.
2. Description of the Related Art
Unlike a hard error, in which a specific portion of a circuit is permanently broken, a soft error is a temporary malfunction that occurs randomly in a semiconductor chip and enables reproduction of an operation. This is caused by a neutron ray of secondary cosmic rays or an alpha ray emanating from an LSI material into an LSI.
Soft errors in latch circuits or flip-flops of logic circuits are acknowledged as a problem. A general countermeasure against soft errors in latch circuits is to provide a latch circuit that retains data at a plurality of nodes (for example, Japanese Patent Application Laid-Open No. 2007-312104).
In recent years, however, as semiconductor chips progressively involve high-integration, the probability of noise due to nuclear radiation at two nodes in the latch circuit increases. When noise is generated at the two nodes in the latch circuit designed to retain data at a plurality of nodes, for example, correct data cannot be maintained. Even when noise is generated at a plurality of nodes at the time of calculating parities of plural latch circuits, the noise can be avoided (for example, Japanese Patent Application Laid-Open No. 2007-248378). However, the circuit design becomes very complicated, the area required for a parity arithmetic circuit becomes very large, and speed is greatly decreased.